1. Technical Field
This disclosure relates to receiver circuits and more particularly, to receiver circuits with a low power mode to reduce power consumption.
2. Description of the Related Art
It is desirable in circuit design to reduce the amount of consumed energy. This is important not only from an energy conservation standpoint, but also to reduce heat effects or limit current density, which may be the cause of degradation in the circuitry, for example, electromigration, or stress failures may be more likely. Many circuits, including integrated circuits have limited energy resources available. For example, devices for mobile communications, other portable devices, such as camcorders, or battery powered devices preferably employ circuitry, which reduces power consumption to reduce the amount of energy consumed by the device.
In one example, receiver circuits, such as differential type receivers, exhibit an amount of significant static power consumption when they are enabled. These devices typically remain active at all times, even if an input signal (for example a data strobe or a clock signal) is not active. This represents an undesirable situation since power may be expended unnecessarily.
Therefore, a need exists for receiver circuits with a power down capability when the input signal is inactive.
A power controlled input receiver, in accordance with the present invention, includes a receiver circuit including a first current source and a second current source. The first current source supplies current in a power down mode of the receiver and the second current source is additionally enabled for supplying current in a normal operation mode. A signal state detection circuit is coupled to the receiver circuit for detecting an active input signal, and a control signal generator is coupled to the signal state detection circuit for generating an enable signal to enable the second current source when the active input signal is detected.
Another power controlled input receiver, in accordance with the present invention, includes a receiver circuit including a first current source and a second current source. The first current source supplies current in a power down mode of the receiver and the second current source is enabled for supplying current in a normal operation mode. A signal state detection circuit is coupled to the receiver circuit. The signal state detection circuit includes an inverter coupled to an output node of the receiver circuit and a current mirror coupled to the inverter and an input state node. The inverter and the current mirror generate pulses on an input state node indicating when the input of the receiver circuit is active. A control signal generator is coupled to the input state node for generating an enable signal in accordance with the pulses to enable the second current source when the input is active.
Yet, another power controlled input receiver of the present invention, includes a receiver circuit including a first current source and a second current source, where the first current source supplies current in a power down mode of the receiver and the second current source is enabled for supplying current in a normal operation mode. A signal state detection circuit is coupled to the receiver circuit, and the signal state detection circuit includes an inverter chain having a first end coupled an output node of the receiver circuit and a second end coupled to a first input of a logic gate. The logic gate has a second input coupled to the output node of the receiver circuit. The logic gate has an output coupled to an input state node. The logic gate generates pulses on an input state node indicating when the input of the receiver circuit is active. A control signal generator is coupled to the input state node for generating an enable signal in accordance with the output of the logic gate to enable the second current source when the input is active.
In alternate embodiments, the receiver circuit may include a differential amplifier. The first current source may include a field effect transistor. The second current source may include a field effect transistor between about 2 and about 10 times larger than the field effect transistor of the first current source. The receiver circuit may include a clock receiver and the input receives clock signals. The first current source of the receiver is active during the power down mode and the normal operation mode. The chain of inverters may include an even number of inverters. The logic may include exclusive OR logic.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.